HD64570 Datasheet, PDF (37/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

RXC
Line input
φ
Receive
clock
selector
000
RXCS2 to RXCS0
(1/1, 1/16*,
(RXS bits 6 to 4)
1/32*, or
Rweithcenivoeiscelockclo1c/k64m*ode)
111
ADPLL
clock
selector
010
110
ADPLL
clock
RXCS2 to 0 ^suppressed
= 010
010
(1/1
(Sampling ^{Clock extractecdlock} mode)
rate:
from receive
operating data
clock
×8,× 16, o×r 32)
110
111
(1/1
clock mode)
Receive
clock
Baud rate
generator
(for
receiving)
f _BRG
=
fφ
TMC
÷
RXBR
2
(TMC: 1 to 256, RXBR:
0
to
9)
100
(1/1,
1/16*,
1/32*, or
1/64*
* Asynchronous
mode
clock mode)
RXCS2 to RXCS0
(RXS bits 6 to 4)
RXS: MSCI RX clock source register
Figure 1.10 Receive Clock Source
Rev. 0, 07/98, page 21 of 453