HD64570 Datasheet, PDF (188/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

CDE0 = 1: Indicates that data is in the top stage of the receive buffer
This register monitors the status of only the top stage of the receive status FIFO in CPU modes 0,
2, and 3, which is different from status register 2 (ST2). ST2 monitors the OR of the status of the
top and second stages of the receive status FIFO. This register is also characterized by its
capability of monitoring the presence/absence of data in the top stage of the receive buffer. As a
result, monitoring this register and current status register 1 (CST1) enables the user to determine
which data status has generated an interrupt, and whether or not the following data can be read by
word. For CST1, see section 5.2.26, MSCI Current Status Register 1 (CST1).
5.2.26 MSCI Current Status Register 1 (CST1)
Current status register 1 (CST1) monitors the second stage of the MSCI's 32-stage status FIFO.
This register indicates whether or not data is in the second stage of the receive buffer, and if there
is any data, indicates the status of the data.
This register is reset under either of the following conditions:
• RX reset command
• Channel reset command
• System stop mode
No bit of this register generates an interrupt.
Async
Byte sync
7
6
5
4
3
2
1
— * _{PMPC1 PEC1 FRMEC1OVRNC1} — * — *
—* —* —*
CRCEC1
Bit sync HDLC EOMC1SHRTC1ABTC1 RBITC1
Read/Write
R
R
R
R
R
R
–
Initial value
0
0
0
0
0
0
0
0
CDE1
R
0
Data status in the second stage of the receive buffer _{Current data 1}
0: No data exists
1: Data exists
Note: The bits marked with * are reserved. These bits always read 0.
Rev. 0, 07/98, page 172 of 453