HD64570 Datasheet, PDF (75/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

CLK (CPU
modes 1, 2, 3)
CLK
(CPU mode 0)
RESET
RD
WR/R/W
A₀ /LDS
BHE/HDS
WAIT
AS
BUSY
D₀ to D₁₅
A₈ to A₂₃
A₁ to A₇
HOLD/
BUSREQ
BEO
INT
Reset mode
6 clock cycles or more
Input
Input
Input
Input
Output
Input
Input (open drain)
High impedance
High impedance
Input
Normal
operating
mode
Figure 3.2 Reset Mode Timing
3.2.4 Normal Operating Mode
In normal operating mode, all functional modules in the SCA are active and communication is
enabled. The SCA operates as follows in this mode:
• The MSCI, DMAC, and timers perform their regular functions with regular performance.
• Interrupt requests (INT) can be generated.
• The SCA can become the bus master through the action of its on-chip bus arbiter.
Rev. 0, 07/98, page 59 of 453