HD64570 Datasheet, PDF (110/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

4.2.8 Interrupt Enable Register 1 (IER1)
The interrupt enable register 1 enables or disables interrupt requests indicated in interrupt status
register 1 (ISR1). All IER1 bits are cleared to 0 at a reset.
7
6
5
4
3
2
1
0
Bit name DMIB3EDMIA3EDMIB2EDMIA2EDMIB1EDMIA1EDMIB0EDMIA0E
Read/Write
Initial value
R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
DMA channel 3
interrupt B enable
0: Disabled
1: Enabled
DMA channel 3
interrupt A enable
0: Disabled
1: Enabled
DMA channel 2
interrupt B enable
0: Disabled
1: Enabled
DMA channel 2
interrupt A enable
0: Disabled
1: Enabled
Note: Initial values are the values after a hardware reset.
DMA channel 0
interrupt A enable
0: Disabled
1: Enabled
DMA channel 0
interrupt B enable
0: Disabled
1: Enabled
DMA channel 1
interrupt A enable
0: Disabled
1: Enabled
DMA channel 1
interrupt B enable
0: Disabled
1: Enabled
Bit 7 (DMIB3E: DMA Channel 3 Interrupt B Enable):
DMIB3E = 0: The DMAC channel 3 DMIB interrupt is disabled.
DMIB3E = 1: The DMAC channel 3 DMIB interrupt is enabled.
Rev. 0, 07/98, page 94 of 453