HD64570 Datasheet, PDF (282/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 6.3 DMAC Operating Modes
Single-Block Transfer Mode
(Single Address)
Chained-Block Transfer Mode (Single Address)
Memory to MSCI
MSCI to Memory
Operating Mode*¹
Memory to MSCI to
MSCI
Memory
Single Frame Multi-Frame Multi-Frame Multi-Frame
Transfer
Transfer
Transfer
Transfer
Requesting source
MSCI
Data transfer unit
Single block
Single frame Multi-frame Single frame Multi-frame
Bus mode
Started by a request from the MSCI
A request from the MSCI is level sensitive
Minimum transfer states/byte
(Word)
3 states
Operation Source
address
Specified by MSCI receiver Specified by the buffer addressMSCI receiver
the source
register (BAR)
address
register (SAR)
Destination
address
MSCI
transmitter
Specified by MSCI transmitter
the destination
address
register (DAR)
Specified by BAR
Transfer Normal The number of bytes of data One frame has The frame One frame 
end
end specified in the byte count been
specified by thehas been
condition
register (BCR) has been
transferred descriptor transferred
transferred
status field
(ST) has been
transferred
Error 
end
A DMA transfer request is issued when the error descriptor
address register (EDA) and current descriptor address register
(CDA) match

Frame end interrupt counter (FCT) overflows when it is
enabled
Available MSCI modes
Asynchronous, byte
synchronous, or bit
synchronous
Bit synchronous*²
Notes: 1. The operating mode is specified using the AMOD and TMOD bits of the DMA mode
register (DMR). For details, see section 6.2.8, DMA Mode Register (DMR).
2. Normal operation is not guaranteed in asynchronous or byte synchronous mode.
Rev. 0, 07/98, page 266 of 453