HD64570 Datasheet, PDF (88/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

CLK
BHE
A₀ to A ₇
CS
T₁ T₂
T₃ T₄ T_i
T₁
T₂ T₃
T₄ T_i
Register address
Register address
RD
WR
WAIT
D₀ to D₁₅
(Out)
D₀ to D₁₅
(In)
Output data
Read cycle SCA ^→MPU
Input data
Data latch point
Write cycle MPU ^→SCA
Note: 1.
2.
Ti states are required between successive slave mode bus cycles or interrupt
acknowledge cycles.
State numbers do not match MPU state numbers.
Figure 3.9 Slave Mode Bus Timing Sequence in CPU Mode 0
Rev. 0, 07/98, page 72 of 453