HD64570 Datasheet, PDF (304/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Start
Yes
CDA = EDA?
No
Load chain pointer
(CP) (16 bits) to DMAC
work register
Load buffer pointer
(BP) (24 bits) to BAR
Load BFL (16 bits)
to BCR
Transfer one byte or one
word, decrement BCR,
and increment BAR
End of
frame detected?
Yes
No
No
BCR = 0?
Yes
Write receive data (DL)
length (16 bits)
Write 00H to status
(ST) field (8 bits)
Load the start address of
the next descriptor from
work register to CDA
Write receive data
length (DL) (16 bits)
Write FST value to
status (ST) field
(8 bits)
Load the start address of
the next descriptor from
work register to CDA
No
Transfer
completed?
Yes
End
(DE bit = 0)
CDA:
EDA:
BFL:
BCR:
FST:
DE bit:
Current descriptor
address register
Error descriptor
address register
Receive buffer length
Byte count register
Frame status register
DMA status register
(DSR) bit 1
Figure 6.19 Operation Flow in MSCI-to-Memory Chained-Block Transfer Mode
Rev. 0, 07/98, page 288 of 453