HD64570 Datasheet, PDF (434/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Register
MSCI (Channel 1)
MSCI Frame Status
Register Channel 1:
FST Channel 1
Not used
MSCI Interrupt Enable
Register 0 Channel 1:
IE0 Channel 1
Address
CPU CPU
Mode Mode
0, 1 2, 3 Remarks
46H 47H
Async
Byte sync
7
6
5
4
3
2
1
0
—— — ——— ——
Bit sync HDLC EOMF SHRTF ABTF RBITF OVRNFCRCEF
Read/Write R/W R/W R/W R/W R/W R/W — —
Initial value
0
0
0
0
0
0
0
0
47H 46H
48H 49H
Frame status at receive completion
7
6
5
4
3
2
1
0
Async
TXINTERXINTE ^—
—
—
— _TXRDYERXRDYE
Byte sync
Bit sync HDLC
Read/Write R/W R/W — — — — R/W R/W
Initial value
0
0
0
0
0
0
0
0
TXINT interrupt
enable
0: Disable
1: Enable
RXINT interrupt
enable
0: Disable
1: Enable
TXRDY interrupt
enable
0: Disable
1: Enable
RXRDY interrupt
enable
0: Disable
1: Enable
Rev. 0, 07/98, page 418 of 453