HD64570 Datasheet, PDF (260/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

6.2.3 Current Descriptor Address Register (CDA: CDAL, CDAH)
One set of two 8-bit subregisters, serving as the current descriptor address register (CDA: CDAL,
CDAH), is provided for each of channels 0, 1, 2, and 3 (figure 6.3).
Single-Block Transfer Mode: In single-block transfer mode, these subregisters are not used.
Their contents have no effect on operation.
Chained-Block Transfer Mode: In chained-block transfer mode, these subregisters serve as the
current descriptor address register (CDA: CDAL, CDAH). This register must be initialized to the
low-order 16 bits of the 24-bit starting address of the descriptor that indicates the first buffer to be
written or read. Later, after a DMA transfer is initiated, the initial value is updated to the starting
address of the next descriptor by the DMAC when the buffers are switched. The high-order eight
bits of the descriptor are specified by the chain pointer base (CPB) and are not updated by the
DMAC.
This register can be read even when a DMA is enabled. For reading this register in byte units,
read CDAL first. Values read from CDAH are those it contained when CDAL was read.
This register must be set in DMA initial state.
After reset, the value of this register is undefined.
H
L
15
87
0
Single-block transfer
mode
Chained-block
transfer mode
Not used
CDAH
Not used
CDAL
Figure 6.3 Current Descriptor Address Register
6.2.4 Error Descriptor Address Register (EDA: EDAL, EDAH)
One set of two 8-bit sub-registers, serving as the error descriptor address register (EDA: EDAL,
EDAH), is provided for each of channels 0, 1, 2, and 3 (figure 6.4).
Single-Block Transfer Mode: In single-block transfer mode, these subregisters are not used.
Their contents have no effect on operation.
Rev. 0, 07/98, page 244 of 453