HD64570 Datasheet, PDF (86/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

3.4 Bus Interface
3.4.1 Overview
The SCA has four 8- and 16-bit bus interfaces that can be switched under external control. The bus
interface is selected according to the CPU mode as shown in table 3.3.
Table 3.3 CPU Mode and Bus Interface
Address Relationships
of Data Bus
Length of Bus Cycle
(number of states)
CPU ModesBus High Byte
Width (D15 to D8)
Low Byte
(D7 to D0)
Slave
Mode*^2, *⁵
Master
Mode MPU Type
Mode 0 16 bits Odd address Even address 4 (5)*³/4 (5)*³ 3*⁴
8086-system
16-bit MPU
Mode 1 8 bits 
All addresses 4/5
3*⁴
64180-type
MPU
Mode 2*¹ 16 bits Even address Odd address 5/6
3*⁴
68000-system
16-bit MPU I
Mode 3*¹ 16 bits Even address Odd address 5/5
3*⁴
68000-system
16-bit MPU II
Notes: 1. CPU modes 2 and 3 differ only in the bus timing. See section 10, Electrical
Characteristics for details.
2. Number of states in read cycle/number of states in write cycle
3. Number of states for consecutive bus cycles in slave mode
4. When no wait states are inserted.
5. Shortest number of states. The number of states may increase if the MPU's strobe
disable timing is delayed.
The SCA has three 16-bit bus interfaces (CPU modes 0, 2, 3). The high-byte/low-byte address
relationship on the data bus in CPU mode 0 is opposite to the relationship in CPU modes 2 and 3.
This gives the SCA a byte-swap capability. The data bus lines map onto even and odd memory
banks as shown in figure 3.8.
Rev. 0, 07/98, page 70 of 453