HD64570 Datasheet, PDF (198/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Reception operation starts when an RX enable command is issued.
In 1/1 clock mode, the receiver searches for a start bit at the rising edge of each clock pulse. On
detecting a space (low level), the receiver begins character assembly at the rising edge of the next
clock pulse.
Character assembly involves assembling a character by loading bit data, which has been sampled
at each clock cycle, into the receive shift register, as shown in figure 5.17.
More specifically, the receiver loads data into the receive shift register so that the data has the
character length specified with the RXCHR1−RXCHR0 bits of MD1, and then samples the parity
or MP bit (if it exists). In the next clock cycle, the receiver samples the stop bit to complete the
character assembly process. Here, the receiver shift register value is loaded into the receive
buffer.
The receiver resumes searching for a start bit one clock cycle after the completion of the character
assembly process.
Receive data
8-bit length
Receive shift register
7-bit length
6-bit length
5-bit length
Shift direction
Sampling clock
7
0
Receive buffer
Figure 5.17 Character Assembly in the Receive Shift Register
Similarly in 1/16, 1/32, or 1/64 clock mode, the receiver searches for a start bit by sampling the
line level at the rising edge of each clock pulse. On detecting a space (low level), the receiver
waits for half a bit cycle, and samples the line level again to verify that the line remains low. If
the line remains low, the receiver starts character assembly after a delay of one bit cycle. If the
line is high, the receiver resumes start bit searching, interpreting the previously detected space as
noise (figures 5.18 (a) and (b)).
Rev. 0, 07/98, page 182 of 453