HD64570 Datasheet, PDF (265/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Bit 6 (EOM: End of Frame Transfer): The function of this bit is described below.
• Single-block transfer mode
Reserved. When read, the value of this bit is undefined. This bit can be set to 0 or 1.
• Chained-block transfer mode
An EOM bit of 1 indicates that a transfer of one frame has been completed normally.
This bit is cleared when a 1 is written to the bit position while the frame end interrupt counter
(FCT) is disabled.
While FCT is enabled and its value is not 0000, the EOM bit remains 1. (See section 6.2.8, DMA
Mode Register (DMR)). At this time, when a 1 is written to this bit, the counter is decremented.
When the counter value becomes 0000, this bit is set to 0. (While FCT is enabled and the EOM
bit is 0, a 1 must not be written to this bit .) The EOM bit is also cleared when a frame end
interrupt counter clear command is issued.
When an FCT overflow occurs, FCT is reset to 0000 and the EOM bit is set to 1. The EOM bit
can be cleared by a frame end interrupt counter clear command specified by the DMA command
register (DCR).
When this bit and the EOME bit of DIR are both 1, the DMAC generates an interrupt request
(DMIB). See the description on the CNTE bit in section 6.2.8, DMA Mode Register, for more
detail.
Bit 5 (BOF: Buffer Overflow/Underflow): The function of this bit is described below.
• Single-block transfer mode
Reserved. When read, the value of this bit is undefined. This bit can be set to 0 or 1.
• Chained-block transfer mode
The BOF bit is set to 1 to indicate that a buffer overflow or underflow occurs in the DMAC. In
this mode, a buffer overflow is defined as the condition when a transfer request is issued by the
MSCI during MSCI-to-memory transfer (reception) while the value of the current descriptor
address register (CDA) and that of the error descriptor address register (EDA) are the same. A
buffer underflow is defined as the condition when a transfer request is issued by the MSCI
during memory-to-MSCI transfer (transmission) while CDA and EDA have the same values.
This bit is cleared when a 1 is written to the bit position.
When this bit and the BOFE bit of DIR are both 1, the DMAC generates an interrupt request
(DMIA). For details, see section 6.2.10, DMA Interrupt Enable Register (DIR).
Rev. 0, 07/98, page 249 of 453