HD64570 Datasheet, PDF (378/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 10.23 Interrupt Timing
(V_CC = 5 V ± 5%, V_SS = 0 V, Ta = 0 to +70°C unless otherwise specified)
Item
INT delay time
Symbol Min Typ Max Unit
t _IRD


35
ns
INTA active set-up time
INTA inactive set-up time
WAIT inactive delay time
WAIT active delay time
Vector data delay time
Vector data hold time
Vector data floating delay time
t _IAS1
t _IAS2
t _IWD1
t _IWD2
t _IDBD1
t _IDBD2
t _IDBZ
15


ns
15


ns


45
ns


50
ns


60
ns
10


ns


60
ns
Timing
Figure 10.10,
figure 10.11
Table 10.24 Bus Arbitration Timing
(V_CC = 5 V ± 5%, V_SS = 0 V, Ta = 0 to +70°C unless otherwise specified)
Item
HOLD delay time
HOLDA set-up time
BEO delay time
Symbol
t _HLDD
t _HLAS
t _BEOD
Min

15

Typ



Max Unit
55
ns

ns
50
ns
BUSY delay time
BUSY set-up time
BUSREQ delay time
BUSACK set-up time
t _BSYD
t _BSYS
t _BRQD
t _BAKS


60
ns
15


ns


50
ns
15


ns
Timing
Figure 10.12
Figure 10.12,
figure 10.13
Figure 10.13
Rev. 0, 07/98, page 362 of 453