HD64570 Datasheet, PDF (209/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Reception Operation: Figure 5.25 is the state transition diagram for reception in byte
synchronous mode.
• RX disable state
The receiver is placed in RX disable state by a hardware reset, a channel reset, an RX reset, or
an RX disable command. In this state, the receiver ignores the input from the RXD line and
does not performs a reception operation.
• SYN1 wait state
The receiver waits for the first byte of the SYN character pattern to establish a character
boundary. If the received data matches the SYN character pattern set in SA0, the receiver
enters character reception state in mono-sync mode or SYN2 wait state in bi-sync mode. In
external synchronous mode, synchronization is established by the SYNC line input.
• SYN2 wait state
The receiver waits for the second byte of the SYN character pattern in bisync mode only. If
the received data matches the SYN pattern set in SA1, the receiver enters character receive
state. If it does not match, the receiver enters SYN1 wait state. The receiver does not enter
SYN1 wait state when in mono-sync or external synchronous mode.
• Character receive state
The receiver transmits the received character to the receive buffer. The SYN character(s) in
the data field may be optionally transmitted to the receive buffer, as specified with the
SYNCLD bit of CTL. The receiver is placed in SYN1 wait state when a message reject
command is issued.
Rev. 0, 07/98, page 193 of 453