HD64570 Datasheet, PDF (261/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Chained-Block Transfer Mode: In chained-block transfer mode, these subregisters serve as the
error descriptor address register (EDA: EDAL, EDAH). This register must be initialized to the
low-order 16 bits of the 24-bit starting address of the descriptor that indicates the buffer next to the
last buffer to be written or read. When the value of the current descriptor address register (CDA)
matches that of EDA, chained-block transfer is terminated. The high-order eight bits of the
descriptor are specified by the chain pointer base (CPB).
This register can be written by the MPU even while a DMA is enabled. For writing this register in
byte units, write EDAL first. When EDAH is written, EDAL and EDAH are updated
simultaneously.
After reset, the value of this register is undefined.
H
L
15
87
0
Single-block transfer
mode
Chained-block
transfer mode
Not used
EDAH
Not used
EDAL
Figure 6.4 Error Descriptor Address Register
Rev. 0, 07/98, page 245 of 453