HD64570 Datasheet, PDF (178/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5.2.20 MSCI Idle Pattern Register (IDL)
The idle pattern register (IDL) specifies the idle pattern output by the transmitter when it is in idle
state.
Async
Byte sync
Bit sync HDLC
Read/Write
Initial value
7
—
IDL7
R/W
1
6
—
IDL6
R/W
1
5
—
IDL5
R/W
1
4
3
2
1
0
—————
IDL4 IDL3 IDL2 IDL1 IDL0
R/W R/W R/W R/W R/W
1
1
1
1
1
Idle pattern
Note: This register is not used in asynchronous mode.
Bits 7−0 (IDL7−IDL0: Idle Pattern): The function of these bits is described below.
• Asynchronous mode
Not used
• Byte synchronous/Bit synchronous mode
When the IDLC bit of the control register (CTL) is 1, the idle pattern set in this register is
output from the TXD line during the idle state. When the IDLC bit is 0, the TXD line is fixed
high.
Rev. 0, 07/98, page 162 of 453