HD64570 Datasheet, PDF (233/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

ADPLL detects no level transition in FM-code receive data in the successive two bit
cycles, or "windows" (from the bit boundary to 1/4 T_B or from 3/4 T_B to the bit boundary),
and the CLMD bit of MSCI status register 1 (ST1) is set to 1.
ADPLL operating clock
(operating mode: x 8)
Receive data
T_B
TD
TC
TB/2 TB/2
Extracted clock
Receive data
syncronized with the
extracted clock
T_S-2
T_S-1
T_S
T_S
T_B:
One receive data bit time
T_C:
One ADPLL operating clock cycle
T_D:
Delay time between the receive data input to the ADPLL and the receive data after
passing the noise suppressor and data delay unit
T_S-1 and T_S-2: Receive data level transitions after noise suppression
T_S:
Synchronized transitions of noise-suppressed receive data after noise suppression.
Figure 5.34 NRZ Receive Data Phase Compensation in Operating Mode × 8
Rev. 0, 07/98, page 217 of 453