HD64570 Datasheet, PDF (316/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 6.11 DMAC Characteristics in CPU Mode 1*¹
Mode
DMA Transfer Rate DMA Transfer DMAC Buffer
Transfer Direction (states/byte)
Set-Up Time*² Switching Time
Single-block Memory to MSCI 3
transfer mode
—
—
MSCI to memory 3
—
—
Chained-block Memory to MSCI 3
transfer mode (transmission)
32*⁷
33/37*⁸
MSCI to memory 3
(reception)
23*⁹
34*¹⁰
Notes: 1 memory cycle = 3 states
Internal states are used for SCA internal operations.
1. Units are states unless otherwise specified. The values shown here are valid when no
wait state is inserted.
2. Before entering a data transfer cycle, the DMAC requires some set-up time to read the
first descriptor.
3. 20 states = 5 memory cycles (15 states) + 5 internal states
4. 21 states = 5 memory cycles (15 states) + 6 internal states (in the middle of a frame)
25 states = 5 memory cycles (15 states) + 10 internal states (at the end of a frame)
5. 18 states = 3 memory cycles (9 states) + 9 internal states
6. 26 states = 5 memory cycles (15 states) + 11 internal states
7. 32 states = 8 memory cycles (24 states) + 8 internal states
8. 33 states = 8 memory cycles (24 states) + 9 internal states (in the middle of a frame)
37 states = 8 memory cycles (24 states) + 13 internal states (at the end of a frame)
9. 23 states = 5 memory cycles (15 states) + 8 internal states
10. 34 states = 8 memory cycles (24 states) + 10 internal states
6.5 Interrupts
The DMAC can issue DMIA (error) and DMIB (normal end) interrupt requests to the MPU.
These requests are indicated by the DMA status register (DSR) and are enabled or disabled by the
DMA interrupt enable register (DIR). Table 6.12 lists interrupt types, interrupt sources, and
clearing their procedures.
Rev. 0, 07/98, page 300 of 453