HD64570 Datasheet, PDF (39/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

1.7.7 Transmitter
The transmitter (figure 1.11) loads parallel data supplied from the data bus into a transmit FIFO
consisting of 32 eight-bit registers. Next, according to the selected transmission format, it moves
the data into a transmit shift register which converts them to serial data. Data are transmitted LSB
first.
1
Stop
bit (1)
Internal data bus
TRB
32-Stage
Transmit EOM/MP bit
buffer
(32-byte FIFO)
command FIFO
(8) (1)
Transmit controller
Transmit shift
BOP, COP
register (8)
Parity
Async ⁽¹⁾
'0' Insertion
To receiver
(local loop back)
Transmit CRC
calculator (16)
Encoder
(1)
From receiver
(local loop back,
auto echo)
TXD
Break send TX pattern
Async
register COP,
BOP
Baud rate
generator
Flag, abort, idle, or SYN
character transmission
COP, BOP
TXC
TRB:
Async:
COP:
BOP:
‡:
MSCI TX/RX buffer register
Asynchronous mode
Byte-synchronous mode
Bit-synchronous mode
Transmit data flow
Numbers in parentheses are bit lengths.
Figure 1.11 Block Diagram of the MSCI Transmitter
Rev. 0, 07/98, page 23 of 453