HD64570 Datasheet, PDF (264/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

7
6
5
4
3
Single-block
transfer mode
Chained-block
transfer mode
—^*1
EOT ^*3
EOM^*3
—^*1
BOF^*3
—^*1
COF^*3
—^*2
Read/Write
Initial value
R/W R/W R/W R/W —
0
0
0
0
0
2
1
0
—^*2 DE DWE
— R/W W
0
0
1
End of transfer
0: Transfer not completed
1: Transfer completed
Counter overflow
• Chained-block
transfer
0: No error detected
1: Error detected
Buffer overflow/underflow
• Chained-block transfer
0: No error detected
1: Error detected
DMA enable
0: Disable
1: ^Enable
DE bit write enable
0: Enable
1: Disable
End of frame transfer
• Chained-block transfer
0: Frame transfer not completed
1: Frame transfer completed
Notes: 1. Reserved. When read, these bits are undefined. They can be set to 0 or 1.
2. Reserved. These bits always read 0 and must be set to 0.
3. These bits can be cleared when a 1 is written to the bit positions.
Bit 7 (EOT: End of Transfer): A 1 indicates that the transfer operation by the DMAC has been
completed normally, in either single-block transfer or chained-block transfer mode. See section
6.4.1, Overview, for the conditions governing DMA normal completion.
This bit is cleared when a 1 is written to the bit position.
When this bit and the EOTE bit of the DMAC interrupt enable register (DIR) are both 1, the
DMAC generates an interrupt request (DMIB). For details, see section 6.2.10, DMA Interrupt
Enable Register (DIR).
Rev. 0, 07/98, page 248 of 453