HD64570 Datasheet, PDF (322/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Bit 7 (CMF: Compare Match Flag): Indicates whether or not the TCNT value matches the
timer constant register (TCONR) value. This bit is cleared when TCNT is read after TCSR. Other
instructions can be inserted between the TCSR and TCNT read instructions. This bit is also
cleared at reset or in system stop mode.
CMF = 0:
Indicates that the TCNT and TCONR values do not match.
CMF = 1:
Indicates that the TCNT and TCONR values match. An interrupt request
(T0IRQ, T1IRQ, T2IRQ, or T3IRQ) is generated when the ECMI bit (bit 6) has been set.
Bit 6 (ECMI: CMF Interrupt Enable): Enables or disables an interrupt request initiated by the
CMF bit. This bit is cleared at reset.
ECMI = 0: Disables an interrupt request initiated by the CMF bit
ECMI = 1: Enables an interrupt request initiated by the CMF bit
Bit 5: Reserved. This bit always reads 0 and must be set to 0.
Bit 4 (TME: Timer Enable): Starts or stops TCNT operation. This bit is cleared at reset or in
system stop mode.
TME = 0:
Stops TCNT, retaining the current TCNT value.
(TCNT resumes incrementing from the retained value, when TME is again set to 1.)
TME = 1:
Starts TCNT.
Bits 3−0: Reserved. These bits always read 0 and must be set to 0.
7.2.4 Timer Expand Prescale Register (TEPR)
The timer expand prescale register (TEPR), provided for each of channels 0, 1, 2, and 3, selects
the expanded clock input for the timer up-counter (TCNT).
Rev. 0, 07/98, page 306 of 453