HD64570 Datasheet, PDF (285/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

CLK
T₁
T₂ (T_W) T₃
BHE, A ₀
A₁ to A ₂₃
D₀ to D₁₅
AS
Read data
Samples data
RD
CLK
T₁
T₂ (T_W) T₃
A₀ to A ₂₃
D₀ to D₇
AS
Memory address
Read data
Samples data
RD
(a) CPU Mode 0
T₁
CLK
T₂ (T_W) T₃
(b) CPU Mode 1
A₁ to A ₂₃
D₀ to D₁₅
AS
Memory address
Read data
Samples data
R/W
HDS,
LDS
(c) CPU Modes 2 and 3
Figure 6.11 External Bus Timing in Memory-to-MSCI Single-Block Transfer Mode
Rev. 0, 07/98, page 269 of 453