HD64570 Datasheet, PDF (267/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

6.2.8 DMA Mode Register (DMR)
The DMA mode register (DMR), provided for each of channels 0, 1, 2, and 3, specifies DMA
transfer mode and number of DMA frames (single or multiple). This register also enables or
disables the frame end interrupt counter (FCT).
This register must be set in DMA initial state.
7
Single-block
transfer mode _—*2
Chained-block
transfer mode
6
5
4
3
—^*2 —^*2 TMOD —^*2
2
1
0
—^*1
CNTE —^*2
NF
Read/Write
Initial value
— — — R/W — R/W R/W —
0
0
0
0
0
0
0
0
DMA transfer mode
0: Single-block transfer
1: Chained-block transfer
Number of DMA frames
• Chained-block transfer
0: Single frame
1: Multi-frame
Frame end interrupt counter (FCT)
enable/disable
• Single-block transfer
Set this bit to 0
• Chained-block transfer
0: Frame end interrupt counter (FCT) disabled
1: Frame end interrupt counter (FCT) enabled
Notes: 1. Reserved. When read, this bit is undefined and can be set to 0 or 1.
2. Reserved. These bits always read 0 and must be set to 0.
Bits 7–5: Reserved. These bits always read 0 and must be set to 0.
Bit 4 (TMOD: DMA Transfer Mode): Specifies the DMAC operation mode in either single-
block transfer mode or chained-block transfer mode as follows. This bit is reset to 0.
TMOD = 0: Specifies single-block transfer mode
TMOD = 1: Specifies chained-block transfer mode
Rev. 0, 07/98, page 251 of 453