HD64570 Datasheet, PDF (155/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5.2.11 MSCI Status Register 2 (ST2)
Status register 2 (ST2) indicates status information such as parity/MP bit value, parity error
detection, and framing error detection in asynchronous mode, CRC error detection in byte
synchronous mode, receive frame end, short frame, abort end frame, residual bit frame, and CRC
error detection in bit synchronous mode, and also indicates overrun error detection in all modes.
This register is located at the top of the 32-stage status FIFO that corresponds to the receive buffer
(figure 1.13). In CPU mode 1, this register is set by the top stage status of the status FIFO. In
CPU modes 0, 2, and 3, this register is set by the OR of the second stage status and the top stage
status of the status FIFO, except when the EOM bit of the top stage is 1. In this case, this register
is set only by the top stage status. Once set to 1, no bit of this register is reset by a status FIFO
change. For the CRCE bit clear conditions, see Bit 2 (CRCE: CRC Error) in this section. Note
that the PMP bit is updated when the next receive character is ready to be read.
The reset descriptions of this register's bits are as follows:
• When 1 is written to a particular bit position, that bit is reset.
• All bits are reset by an RX or a channel reset command.
• All bits are reset in system stop mode.
• All bits are reset when data is transferred to the frame status register (FST) (See section
5.2.13, MSCI Frame Status Register (FST)).
When any bit of this register is set to 1, an MPU interrupt request is generated (if enabled).
Rev. 0, 07/98, page 139 of 453