HD64570 Datasheet, PDF (333/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

PAH: FFFFFFH (upper limit address) to 400000H (lower limit address)
PAM: 3FFFFFH (upper limit address) to 010000H (lower limit address)
PAL: 00FFFFH (upper limit address) to 000000H (lower limit address)
Physical address boundary
register 1 (PABR1)
PABR1 value: 40 H
FFFFFFH
400000H
3FFFFFH
PAH area
PAM area
Physical address boundary
register 0 (PABR0)
PABR0 value: 01 H
010000H
00FFFFH
000000H
PAL area
Physical address space
Figure 8.1 Memory Space Partitioned by PABR0 and PABR1
When either PABR0 or PABR1 is set to 00H, the boundary is at the top of the memory space.
Accordingly, when PABR1 is set to 00H and PABR0 is set to 01H, each area is specified as
follows:
PAH: 
PAM: FFFFFFH (upper limit address) to 010000H (lower limit address)
PAL: 00FFFFH (upper limit address) to 000000H (lower limit address)
Note that the memory space consists of only PAL and PAM because the PAM upper limit address
is FFFFFFH.
Figures 8.2 (a) to 8.2 (d) show examples of when the physical address space is not partitioned,
when it is partitioned into PAM and PAL, into PAH and PAL, and into three areas (PAH, PAM,
and PAL), respectively.
Rev. 0, 07/98, page 317 of 453