HD64570 Datasheet, PDF (388/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 10.34 CPU Mode 1 Master Mode Bus Timing
(V_CC = 5 V ± 10%, V_SS = 0 V, Ta = −40 to +85°C unless otherwise specified)
Item
Clock cycle time
Clock high-level pulse width
Clock low-level pulse width
Clock fall time
Clock rise time
Address delay time
Address set-up time
AS delay time 1
RD delay time 1
Address hold time
AS delay time 2
RD delay time 2
Data read set-up time
Data read hold time
WAIT set-up time
WAIT hold time
Write data floating delay time
WR delay time 1
Write data delay time
Write data set-up time
WR delay time 2
WR pulse width
Write data hold time
AS high-level pulse width
AS low-level pulse width
Symbol
t _CYC
t _CHW
t _CLW
t _cf
t _cr
t _AD
t _AS
t _ASD1
t _RDD1
t _AH
t _ASD2
t _RDD2
t _DRS
t _DRH
t _WS
t _WH
t _WDZ
t _WRD1
t _WDD
t _WDS
t _WRD2
t _WRP
t _WDH
t _ASWH
t _ASWL
Min
125
50
50



20


10


25
5
30
30



15

110
10
70
80
Typ

























Max Unit
2000 ns

ns

ns
10
ns
10
ns
55
ns

ns
50
ns
50
ns

ns
50
ns
50
ns

ns

ns

ns

ns
60
ns
50
ns
60
ns

ns
55
ns

ns

ns

ns

ns
Timing
Figure 10.7
Rev. 0, 07/98, page 372 of 453