HD64570 Datasheet, PDF (227/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5.5 ADPLL
5.5.1 Overview
The advanced digital PLL (ADPLL) extracts clock signals from the receive data and generates a
decoding clock for the receive data.
The ADPLL features:
• Clock extraction from five transmission code types (figure 1.8)
 NRZ
 NRZI
 Manchester
 FM0
 FM1
• Selectable ratio of the ADPLL clock rate to the bit rate
 ×8
 × 16
 × 32
• Receive data noise suppression (see section 5.5.2, Operation)
• Receive clock noise suppression (see section 5.5.2, Operation)
Figure 5.32 is the block diagram of the ADPLL.
Receive
data
ADPLL
operating
Receive BRG
output
clock
External clock
(RXC line input)
Clock
line 1
Receive data
noise
suppressor
Data
delay unit
Noise-suppressed
receive data
Receive data in
phase with the
extracted clock
Multiplexor
Clock extractor Extracted clock
Clock
line 2
Receive clock
noise
suppressor
Noise-suppressed
receive clock
Figure 5.32 ADPLL Block Diagram
The ADPLL can perform either clock extraction from the receive data or noise suppression for the
receive clock input from the RXC line. In both cases it suppresses the receive data noise.
Rev. 0, 07/98, page 211 of 453