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| HD64570 Datasheet, PDF (127/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor | |||
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CRC0 = 1: Specifies all 1s as the CRC calculator initial value
The following CRC bit patterns are sent starting with the most significant bit.
Protocol
CRC-16
Preset 0
CRC-CCITT
Preset 0
CRC-16
Preset 1
CRC-CCITT
Preset 1*1
BOP (bit synchronous Complemented*2 Complemented*2 Complemented*2 Complemented*2
mode)
COP (byte
Not
Not
Not
Not
synchronous mode) complemented complemented complemented complemented
Notes: 1. CRC-CCITT preset 1 is recommended for the HDLC modes in such recommendations
LAPB and X.25.
2. One's complement
5.2.2 MSCI Mode Register 1 (MD1)
Mode register 1 (MD1) specifies the transmit/receive character length, the parity/MP bit, and the
relationship between the transmit/receive data and the transmit/receive clock, all in asynchronous
mode. This register also specifies the checking method for the address field in bit synchronous
mode. This register does not function in byte synchronous mode. For the parity/MP bit, see
section 5.3, Operations.
This register is reset under either of the following conditions:
⢠Hardware reset
⢠Channel reset command
Rev. 0, 07/98, page 111 of 453
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