HD64570 Datasheet, PDF(118/469 Page) Hitachi Semiconductor – Serial Communications Adaptor

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HD64570 Datasheet, PDF (118/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

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ï£§ Programmable parity (odd, even, or no parity)

ï£§ Detection of parity, overrun, and framing errors

ï£§ Break transmission and reception

ï£§ Multiprocessor (MP) bit transmission and reception

ï£§ Programmable bit rate (input clock frequency Ã 1/1, 1/16, 1/32, or 1/64)

â¢ Byte Synchronous Mode

ï£§ 8-bit character length

ï£§ Mono-sync, bi-sync, and external synchronous modes supported

ï£§ CRC code generation and check. Initial value (all 0s or 1s) selectable for each of CRC-16

and CRC-CCITT generator polynomials

ï£§ Automatic SYN character transmission, detection, and deletion

ï£§ CRC code transmission or no-transmission in underrun state program-selectable

ï£§ SYN character or mark transmission in idle state program-selectable

ï£§ Detection of CRC, overrun, and underrun errors

â¢ Bit Synchronous Mode

ï£§ 8-bit character length

ï£§ HDLC mode supported

ï£§ Information (I) field configured in bytes

ï£§ Automatic zero insertion in transmit data and deletion from receive data

ï£§ Flag or mark transmission program-selectable in idle state

ï£§ 8- or 16-bit address (A) field selectable; Four address field check modes program-

selectable

ï£§ End-of-message detection

ï£§ CRC code generation and detection

5.1.2 Configuration and Operation

The MSCI block diagram is shown in figure 1.2.

The MSCI has 27 internal registers that the user can access. These registers specify the operating

mode and control transmission and reception operations.

Receiver: The following describes the operations of the MSCI receiver, referring to figure 1.13.

The MSCI receiver has one 32-stage FIFO receive buffer, five 8-bit shift registers, and one delay

register. The receiver also has a 6-bit status buffer (FIFO). This buffer retains status information,

such as parity or framing errors, related to the received data. Note that status register 2 (ST2) and

current status registers 0 and 1 (CST0 and CST1) are located at the top of the status buffer (FIFO)

and interface with the internal data bus. For details, see sections 5.2.11, MSCI Status Register 2

Rev. 0, 07/98, page 102 of 453

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