HD64570 Datasheet, PDF (80/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Figure 3.4 shows the interconnections of the bus arbiter and bus masters.
Bus control signals
Data bus and address bus
DMAC
MPU
Bus
arbiter
HOLD/
BUSREQ
HOLDA/BUSACK
BUSY
BEO
Other bus
master
Bus
request
SCA
(DMAC: DMA controller)
Figure 3.4 Bus Arbiter and Bus Masters
3.3.2 Timing for Passing Bus Control
If BUSACK becomes inactive (high) (HOLDA becomes low in CPU mode 0) during a DMA
transfer, the bus arbiter releases control of the bus at an opportunity furnished by the on-chip
DMAC controller.
The on-chip DMAC controller allows control of the bus to pass to another bus master at the end of
each machine cycle, immediately after a T₃ or T_i state. See section 6, DMAC, for details. When
BUSACK (HOLDA in CPU mode 0) becomes inactive, the on-chip DMAC suspends the transfer
at the end of a machine cycle and makes BUSY inactive (high), passing control of the bus to
another bus master. If BUSACK (HOLDA in CPU mode 0) later becomes active low (high in
CPU mode 0), the DMAC waits for BUSY to become inactive, then takes control of the bus and
resumes the transfer.
3.3.3 Bus Control Passing
Figure 3.5 shows how bus control is passed.
Rev. 0, 07/98, page 64 of 453