HD64570 Datasheet, PDF (67/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 2.7 System Control Lines
Pin Number
Symbol
HOLD/
BUSREQ
CP-84
77
FP-88
4
HOLDA/ 78
5
BUSACK
BEO
79
6
Input/
Output
Description
Output CPU mode 0
Input
Hold: Used to request the bus. By driving HOLD
active high, the SCA asks the host MPU to
grant control of the bus.
CPU modes 1, 2, 3
Bus request: Used to request the bus. By
driving BUSREQ active low, the SCA asks the
host MPU to grant control of the bus.
CPU mode 0
Output
Hold acknowledge: Used to indicate that the
host MPU has received a HOLD signal and
released the bus. When HOLDA is driven active
high, the SCA assumes that control of the bus
has been granted.
If this line goes low (inactive) during a DMA
transfer, the SCA releases control of the bus at
the next bus cycle at which such release is
permitted.
CPU modes 1, 2, 3
Bus acknowledge: Used to indicate that the
host MPU has received a BUSREQ signal and
released the bus. When BUSACK is driven
active low, the SCA assumes that control of the
bus has been granted.
If this line goes high (inactive) during a DMA
transfer, the SCA releases control of the bus at
the next bus cycle at which such release is
permitted.
Bus enable output: Used for daisy-chained bus
arbitration. When the HOLD or BUSACK line is
active, unless an internal DMA transfer request
is present in the SCA, BEO is driven active low
to pass the acknowledgment on to a lower-
order device.
Rev. 0, 07/98, page 51 of 453