HD64570 Datasheet, PDF (270/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

6.2.10 DMA Interrupt Enable Register (DIR)
The DMA interrupt enable register (DIR), provided for each of channels 0, 1, 2, and 3, enables or
disables transfer end interrupts, frame transfer end interrupts, buffer overflow/underflow
interrupts, and counter overflow interrupts.
7
6
5
4
3
2
1
0
Single-block
transfer mode
—^*1
Chained-block ^EOTE
—^*1
—^*1
—^*2
—^*2 —^*2
—^*2
transfer mode
EOME BOFE COFE
Read/Write R/W R/W R/W R/W — — — —
Initial value
0
0
0
0
0
0
0
0
Transfer end interrupt
enable
0: Disable
1: Enable
Counter overflow
interrupt enable
• Chained-block transfer mode
0: Disable
1: Enable
Frame transfer end interrupt
enable
• Chained-block transfer mode
0: Disable
1: Enable
Buffer overflow/underflow
interrupt enable
• Chained-block transfer mode
0: Disable
1: Enable
Notes: 1. Reserved. When read, these bits are undefined and can be set to 0 or 1.
2. Reserved. These bits always read 0 and must be set to 0.
Bit 7 (EOTE: Transfer End Interrupt Enable): Enables or disables a DMA normal end
interrupt (DMIB) caused by the EOT bit of DSR in either single-block transfer mode or chained-
block transfer mode as follows.
EOTE = 0: Disables an interrupt (DMIB) caused by the EOT bit
EOTE = 1: Enables an interrupt (DMIB) caused by the EOT bit
Bit 6 (EOME: Frame Transfer End Interrupt Enable): The function of this bit is described
below.
• Single-block transfer mode
Rev. 0, 07/98, page 254 of 453