HD64570 Datasheet, PDF (195/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Reception Operation: Figure 5.15 is the state transition diagram for reception in asynchronous
mode.
• RX disable state
The receiver is placed in RX disable state by a hardware reset, a channel reset, an RX reset, or
an RX disable command. In this state, the receiver ignores the input from the RXD line and
does not perform a reception operation. The contents of the receive shift register are lost, but
the value of the receive buffer is not affected.
• Start bit search state
RX enable sets the receiver in start bit search state from RX disable state. In the start bit
search state, the receiver samples the RXD line level at the rising edge of each receive clock
pulse until a low level is detected.
• Start bit check state
On detecting a low level while in start bit search state, the receiver enters start bit check state.
In this state, the receiver waits for half a bit cycle and then samples the RXD line again. If the
line is still low, the receiver enters character assembly state. If the line is not low, the receiver
returns to start bit search state. If the line remains at space, the receiver enters character
assembly state.
In 1/1 clock mode, the RXD line is not retested, and the receiver enters character assembly
state immediately after space detection.
• Character assembly state
The receiver samples the received data at each bit cycle and assembles a character. The
receiver ends character assembly when the first stop bit is detected.
• Half-bit cycle wait state
If a framing error occurs after character assembly, the receiver waits for half a bit cycle in
order to skip the stop bit associated with the framing error, and then enters start bit search state.
For details on a framing error, see Error Checking in this section.
• Break end wait state
On detecting a break after character assembly, the receiver enters break end wait state, where it
samples the RXD line level at each clock cycle until the line goes high (mark).
For details on a break, see Break Transmission and Detection.
• Break end check state
On detecting a high level while in break end wait state, the receiver enters break end check
state. In this state, the receiver waits for half a bit cycle and then samples the RXD line level
again. If the line remains high, the receiver enters start bit search state. If the line does not
remain high, the receiver returns to break end wait state.
In 1/1 clock mode, the RXD line is not retested, and the receiver enters start bit search state
immediately after mark detection.
Rev. 0, 07/98, page 179 of 453