HD64570 Datasheet, PDF (275/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Bit 3 (CCC: Channel Change Condition): Specifies the condition for switching bus control
between channels in either single-block transfer mode or chained-block transfer mode as follows.
Bus control changes immediately after T₃ or T_i state of each cycle (transmit/receive data transfer
cycle or the cycles shown in figure 6.22).
CCC = 0: One channel releases the bus to another channel at each cycle
CCC = 1: One channel releases the bus to another channel when all DMA requests for the channel
have been processed
Bits 2–0 (PR2–PR0: Channel Priority): Specify channel priority on the bus control in either
single-block transfer mode or chained-block transfer mode as follows.
PR2, PR1, PR0 = 0, 0, 0: Priority = Channel 0 > channel 1 > channel 2 > channel 3
PR2, PR1, PR0 = 0, 0, 1: Priority = Channel 2 > channel 3 > channel 0 > channel 1
PR2, PR1, PR0 = 0, 1, 0: Priority = Channel 0 > channel 2 > channel 1 > channel 3
PR2, PR1, PR0 = 0, 1, 1: Priority = Channel 1 > channel 3 > channel 0 > channel 2
PR2, PR1, PR0 = 1, ×, ×: Priority = Channel 0 ‡ channel 1 ‡ channel 2 ‡ channel 3 ‡ channel 0
(rotation) (“×” indicates either 0 or 1)
DMA transfers by multiple channels with PR2 = 1, BRC = 1, and CCC = 1 is described below.
1. When the SCA has obtained bus control, channels that request their first DMA transfer are
serviced, according to the priority specified.
2. When a different channel requests its first DMA transfer during the DMA transfer initiated in
step 1:
a. If a channel with a lower priority requests its first DMA transfer when a channel with a higher
priority is performing its DMA transfer, the specified priority is obeyed.
b. If a channel with a higher priority requests its first DMA transfer when a channel with a lower
priority is performing its first DMA transfer, the higher priority channel must wait until the
channel with the lowest priority in step 1 has completed its DMA transfer.
a or b applies also when multiple channels request their first DMAs.
3. The SCA releases the bus when every channel that requested a first DMA transfer has
completed its DMA transfer, except when a channel requests a second DMA transfer before the
above procedure is completed. In this case, the SCA repeats the above procedure, beginning with
the step when the SCA obtains bus control.
Rev. 0, 07/98, page 259 of 453