HD64570 Datasheet, PDF (212/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

• Underrun error
An underrun error occurs when the transmit buffer is empty after data has been sent from the
transmit shift register.
When an underrun error occurs, the transmitter enters idle state. (The MSCI assumes an
underrun error when the transmit shift register and transmit buffer are both empty and an end
of message command has not been issued.) The transmitter then drives the TXD line high
(when the IDLC bit of CTL is 0), or outputs an idle pattern (when the IDLC bit is 1). Here, the
transmitter can transmit the CRC code before entering idle state if the UDRNC bit of CTL is
set to 1. If an underrun error occurs when UDRNC or CRCCC is 0, the transmitter directly
enters idle state without transmitting the CRC code.
After entering idle state, the transmitter enters SYN1 transmit state when the UDRN bit is
cleared and when data is written to the transmit buffer.
When an underrun error occurs, the UDRN bit of ST1 is set to 1, and the TXRDY bit of ST0 is
cleared. This generates an interrupt request (if enabled). The UDRN bit is cleared only when
a 1 is written to the bit position or ST1 is reset.
Message End Operation: During transmission, the MSCI recognizes the end of message when it
executes an end of message command. Also, the MSCI automatically assumes an end of message
when an underrun error occurs while the UDRNC bit of CTL is 1.
When the CRCCC bit of MD0 is 1 when the message transmission is completed, the transmitter
automatically transmits a CRC code and then enters idle state. When the CRCCC bit is 0 when
the message transmission is completed, the transmitter enters idle state without CRC code
transmission, and an interrupt request is generated (if enabled).
During reception, the receiver does not detect the end of message.
Rev. 0, 07/98, page 196 of 453