HD64570 Datasheet, PDF (328/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

φ
Timer up-
counter
(TCNT)
CMF
TCNT = TCONR
T0IRQ, T1IRQ,
T2IRQ, T3IRQ
TCNT = 0000H
TCNT = 0001H
1 clock
Read TCSR after interrupt processing
Read TCNT
φ: Internal clock
TCNT: Timer up-counter
TCONR: Timer constant register
TCSR: Timer control/status register
CMF: Bit 7 of TCSR
T0IRQ to T3IRQ: Timer interrupt requests
Figure 7.4 Interrupt Timing (when the counter operating rate is BC)
7.5 Operation in System Stop Mode
In system stop mode, the following events occur:
• The CMF and TME bits of the timer constant/status register (TCSR) are cleared.
• TCSR and the timer expand prescale register (TEPR) retain their current contents, except the
CMF and TME bits of TCSR.
• The timer up-counter (TCNT) stops and is initialized to 0000H.
• No interrupt request is generated.
System stop mode is canceled by RESET input; TEPR is cleared simultaneously.
7.6 Reset Operation
The timers are initialized at reset as follows:
• The timer control/status register (TCSR) and the timer expand prescale register (TEPR) are
initialized to 0000H.
• The timer up-counter (TCNT) stops and is initialized to 0000H.
• The timer constant register (TCONR) is initialized to FFFFH.
• No interrupt request is generated.
Rev. 0, 07/98, page 312 of 453