HD64570 Datasheet, PDF (243/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

TMC
f_BRG: Transmit (receive) BRG output frequency
f_CLK: System clock frequency (frequency equal to f_BRG can be used only for the
ADPLL operating clock)
TMC: Value (1−256) set in TMC
BR: Value (0−9) of TXBR3−TXBR0 bits of TXS or RXBR3−RXBR0 bits of RXS
Table 5.20 gives widths and duty ratios (pulse width to pulse period) of BRG output clock
waveforms along with the corresponding register set values.
Table 5.20 BRG Output Waveform and Register Set Values
Set Value
BR TMC Waveform
1−9  Duty ratio = 50%
0
≠ 1 Duty ratio = 50% when TMC = 2
Duty ratio ≠ 50% when TMC ≠ 2
Pulse width is 1 system clock cycle
1 system
clock cycle
= 1 Duty ratio = 50%
Cycle width is 1 system clock cycle
1 system
clock cycle
BR: Value of bits 3−0 of the TXS or RXS
TMC: Value of bits 7−0 of the TMC
5.6.3 Register Set Values and Bit Rates
Asynchronous Mode: In asynchronous mode, the bit rate is selected with TMC7−TMC0 bits of
the time constant register (TMC), the TXBR3−TXBR0 bits of the TX clock source register (TXS),
Rev. 0, 07/98, page 227 of 453