HD64570 Datasheet, PDF (185/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5.2.23 MSCI TX Ready Control Register 0 (TRC0)
TX ready control register 0 (TRC0) determines the MSCI TX ready (TXRDY) activation
condition. The function of this register is the same in asynchronous, byte synchronous, and bit
synchronous modes.
7
Async
—
Byte sync
Bit sync HDLC
Read/Write
—
Initial value
0
6
5
4
3
2
1
0
— — TRC04 TRC03 TRC02 TRC01 TRC00
— — R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
TX ready control 0 (TXF0)
Note: Bits 7–5 are reserved. These bits always read 0 and must be set to 0.
Bits 7−5: Reserved. These bits always read 0 and must be set to 0.
Bits 4−0 (TRC04−TRC00: TX Ready Control 0): Determine the MSCI TX ready (TXRDY)
activation condition. When the data byte count in the transmit buffer is equal to or less than
TXF0, that is, the value set by these bits, TX ready is activated. In other words, the TXRDY bit of
status control register 0 (ST0) is set to 1. Any value can be set in the range from 00H−1FH.
Rev. 0, 07/98, page 169 of 453