HD64570 Datasheet, PDF (101/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Bit 7 (IPC: Interrupt Priority Control): Controls the priority order of interrupt sources. This bit
is cleared to 0 at a reset.
IPC = 0: MSCI interrupt sources have higher priority than DMAC interrupt sources.
IPC = 1: DMAC interrupt sources have higher priority than MSCI interrupt sources.
Bit 6, Bit 5 (IAK1, IAK0: Interrupt Acknowledge Cycle): Select the type of acknowledge
cycle. These bits are cleared to 0 at a reset.
IAK1, IAK0 = 0, 0:
Non-acknowledge cycle; the data bus is left in the high-impedance state
even when the INTA line is driven active low. Although the INTA line
input is ignored if this type of acknowledge cycle is selected, this line
should be pulled up to V_CC.
IAK1, IAK0 = 0, 1:
Single acknowledge cycle; the value in IVR or IMVR is output on data
bus lines D₇ to D₀ at the first active (low) input on the INTA line. Output for D₁₅ to D₈ is
undefined.
IAK1, IAK0 =1, 0:
Double acknowledge cycle; the data bus is left in the high-impedance state
at the first active (low) input on the INTA line. The value in IVR or IMVR
is output on data bus lines D₇ to D₀ at the second active (low) input on the
INTA line. Output for D₁₅ to D₈ is undefined.
IAK1, IAK0 =1, 1: Reserved.
Bit 4 (VOS: Vector Output Select): Selects which vector to output in a single or double
acknowledge cycle. This bit is cleared to 0 at a reset.
VOS = 0: The interrupt vector register is selected. The unmodified IVR contents are output in a
single or double acknowledge cycle.
VOS = 1: The interrupt modified vector register is selected. The IMVR contents are output in a
single or double acknowledge cycle.
Bits 30: Reserved. These bits always read 0 and must be set to 0.
Rev. 0, 07/98, page 85 of 453