HD64570 Datasheet, PDF (122/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

• Asynchronous/Byte synchronous/Bit synchronous mode
AUTO = 0: Specifies CTS and DCD as general-purpose inputs, and RTS as a general-
purpose output.
CTS, DCD, and RTS have no effect on MSCI transmission or reception
AUTO = 1: Sets the auto-enable function. CTS, DCD, and RTS serve as modem control
signals for an RS-232C interface or the like. (Note that the auto-enable function of CTS and
DCD is available in any operating mode (asynchronous, byte synchronous, or bit synchronous
mode), while the function of RTS is available only in asynchronous mode.
For example, the CTS input controls transmission operations. In asynchronous mode, when
the CTS input goes high, the transmitter sends the data from the transmit shift register, then
enters idle state with TXD held high. In idle state, no data is transferred from the transmit
buffer to the transmit shift register. In byte or bit synchronous mode, when the CTS input goes
high, the transmitter sends the data from the transmit shift register, then stops transferring data
to this register from the transmit buffer. This generates an underrun error (the UDRN bit of
ST1 register is set), and the transmitter enters the idle state according to the sequence specified
by the UDRNC bit of the MSCI control register (CTL).
The DCD input controls reception operations. When DCD is high, reception is disabled. If
DCD goes high during character assembly, the data being assembled is lost. However, the data
in the receive buffer remains intact. (Character assembly implies sampling of received data
and assembly of a character in the receive shift register.)
The RTS output is low during transmission in asynchronous mode. Otherwise (when TX is
disabled or in idle state), the RTS line outputs the value of the RTS bit of the control register
(CTL). In byte or bit synchronous mode, the RTS output is independent of transmission
operation and the RTS line outputs the value of the RTS bit of the control register (CTL).
The timing for modem control signal RTS is shown in figure 5.1 (a) to figure 5.1 (h). The RTS
output goes high one clock cycle after the TXD line has been set to "mark" after data
transmission (figure 5.1 (a)). The RTS output during data write to the transmit buffer (TRB)
by the MPU is shown in figure 5.1 (b) to figure 5.1 (e). The RTS output during data
transmission to the transmit buffer (TRB) in DMA cycles is shown in figure 5.1 (f) to figure
5.1 (h).
Rev. 0, 07/98, page 106 of 453