HD64570 Datasheet, PDF (159/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Reserved. This bit always reads 0 and can be set to 0 or 1.
• Byte synchronous/Bit synchronous mode
The CRCE bit indicates whether or not a CRC error has occurred. When the CRCCC bit of
MD0 is 1, this bit is set to 1 when a CRC error occurs. When the CRCCC bit is 0, this bit is
not set to 1.
This bit is cleared when 1 is written to this bit position or when the CRC calculation result is
normal. This bit is the only bit of ST2 that changes status as the status FIFO changes status.
For the timing of enabling this bit, see CRC errors, in Error Checking in sections 5.3.2, Byte
Synchronous Mode and 5.3.3, Bit Synchronous Mode.
CRCE = 0: Indicates that no CRC error has occurred
CRCE = 1: Indicates that a CRC error has occurred
Bits 1−0: Reserved. These bits always read 0 and can be set to 0 or 1.
Residual bit frame reception operation: A residual bit frame reception operation is shown in
figure 5.3. Residual bit frame data is transferred from the receive shift register to the receive
buffer, and the residual bit frame status is set in the status FIFO.
Status
Receive buffer FIFO
Empty
Data 1 (8)
Data 2 (8)
Receive buffer
MSB
LSB
Status
FIFO
Data 1 (8)
Data 2 (8)
Residual
bit data (6)
EOM = 1
RBIT = 1
Flag (8)
Receive shift register
FCS2 (8)
FCS1 (8)
Residual
bit data (6)
FCS: Frame check sequence
( ): Bit count
Figure 5.3 Residual Bit Frame Reception Operation (CRCCC = 1)
1. Residual bit data is transferred from the receive shift register to the receive buffer. At this time,
the bits other than the residual data are undefined.
2. The EOM and RBIT bits of the status FIFO are set to 1.
Rev. 0, 07/98, page 143 of 453