HD64570 Datasheet, PDF (359/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

10.1.3 AC Characteristics
Table 10.3 CPU Mode 0 Slave Mode Bus Timing
(V_CC = 5 V ± 10%, V_SS = 0 V, Ta = −20 to +75°C unless otherwise specified)
Item
Symbol Min Typ Max Unit Timing
CS set-up time
CS hold time 1
CS hold time 2
t _CSS
t _CSH1
t _CSH2
30


ns
Figure 10.1
20


ns
0


ns
Address set-up time
t _ADS
30


ns
Address hold time
RD active set-up time
RD inactive set-up time
RD inactive hold time
RD active hold time
WR active set-up time
WR inactive set-up time
WR inactive hold time
WR active hold time
t _ADH
0


ns
t _RDS1
30


ns
t _RDS2
30


ns
t _RDH1
10


ns
t _RDH2
0


ns
t _WRS1
30


ns
t _WRS2
30


ns
t _WRH1
10


ns
t _WRH2
0


ns
WAIT active delay time
t _WTD1


50
ns
WAIT inactive delay time
t _WTD2


50
ns
Read data active delay time
t _DBD1


65
ns
Read data hold time
t _DBD2
10


ns
Read data floating delay time
t _DBZ


60
ns
Write data set-up time
t _DBS
25


ns
Write data hold time
t _DBH
20


ns
Notes: 1. The CLK timing is the same in this mode and DMA mode. See table 10.7.
2. For the measurement conditions of AC characteristics, see figure 9.25.
Rev. 0, 07/98, page 343 of 453