HD64570 Datasheet, PDF (374/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 10.19 CPU Mode 3 Slave Mode Bus Timing
(V_CC = 5 V ± 5%, V_SS = 0 V, Ta = 0 to +70°C unless otherwise specified)
Item
Symbol Min Typ Max
Address set-up time
t _ADS
15


Address hold time
t _ADH
0


AS set-up time
t _ASS
15


AS hold time
t _ASH
0


CS set-up time
t _CSS
15


CS hold time
t _CSH
0


HDS, LDS active set-up time
t _DSS1
15


HDS, LDS inactive set-up time
t _DSS2
10


HDS, LDS inactive hold time
t _DSH1
10


HDS, LDS active hold time
t _DSH2
0


R/W set-up time
t _RWS
15


R/W hold time 1
t _RWH1
0


R/W hold time 2
t _RWH2
0


WAIT inactive delay time
t _WTD1


50
WAIT active delay time
t _WTD2


50
Read data active delay time
t _DBD1


60
Read data hold time
t _DBD2
10


Read data floating delay time
t _DBZ


60
Write data set-up time
t _DBS
15


Write data hold time
t _DBH
20


Write data WAIT hold time
t _DBWH
0


Note: The CLK timing is the same in this mode and DMA mode.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Timing
Figure 10.4
Rev. 0, 07/98, page 358 of 453