HD64570 Datasheet, PDF (306/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 6.7 Control Registers Used in MSCI-to-Memory Chained-Block Transfer Mode
(reception) (cont)
Register Receive Buffer Length
Name
(BFL)
Register Initialized before reception.
updated by
the MPU
Number of 16
bits
Function Indicates the buffer length
in bytes.
Role in —
DMAC
operation
Register Under MPU control.
update
Register Initialized.
updated by
the MPU
Byte Count Register
(BCR)
Buffer Address
Register (BAR)
Loaded with the start
When reception begins,
address of the descriptor indicates the start
indicating the buffer following address of the descriptor
the last write buffer. When which indicates the buffer
releasing the buffer, this
to be written.
register indicates the start
address of the descriptor for
the buffer following the one
being released.
16
24
Indicates the byte count of
the data remaining in the
buffer waiting to be written
to memory. Writing to this
register by the MPU is
prohibited.
Indicates the system
memory address of the
data being loaded into
the buffer. Writing to this
register by the MPU is
prohibited.
When the contents of this When a transfer request
register equal 0000H, writing is issued, data is loaded
to the current buffer stops. into the address specified
by this register.
The contents are
decremented each time
one byte or one word is
written. When the buffer
is switched, the BFL value
is loaded.
The contents are
incremented each time
one byte or one word is
written. When the buffer
is switched, the next
buffer start address is
loaded.
—
—
Table 6.8 shows a typical MSCI-to-memory chained-block multi-frame transfer using four
descriptors and four buffers. In this example, after a transfer begins, CDA is updated and then the
CDA initial value is written to EDA since transfer is disabled when CDA and EDA are equal. As
a result, the write-enabled buffer size is maximized. In this example, the CDA and EDA values
match after frame 2 has been transferred (step 9). At this time, any additional transfer request is
disabled and interrupt DMIA is generated (if enabled).
Rev. 0, 07/98, page 290 of 453