HD64570 Datasheet, PDF (200/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

In the character assembly process, the receiver samples data every other bit cycle. On detecting
the most significant bit (MSB) or the parity bit (if present), the receiver checks the stop bit after a
delay of one bit cycle. If the RXD line is high (normal), the receiver begins start bit searching
immediately. If the line is low (framing error), the receiver begins start bit searching after a delay
of half a bit cycle.
In 1/16, 1/32, or 1/64 clock mode, the noise suppression function operates for start bit, character,
parity bit, and stop bit sampling.
The noise suppression function operates by using the RXD line level that occurs in two of three
sampling timings, which are the current sampling timing and the two preceding sampling timings
(figure 5.19).
Start bit search
Start bit detected
Start bit check
Receive clock
Receive line
Sampling data
Figure 5.19 Noise Suppression Function
In asynchronous mode, the receivable character length is 8 to 5 bits, which is specified with the
RXCHR1−RXCHR0 bits of MD1.
Figure 5.20 shows the receive data format. When the character length is 7 to 5 bits, the high-order
bits are padded with 0s.
Rev. 0, 07/98, page 184 of 453