HD64570 Datasheet, PDF (240/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 5.19 ADPLL Receive Margin (theoretical values; see note 1)
Code Type Operating Mode
Bit Margin (t - t₀)/t₀
Bit Rate Margin (t - t₀)/t₀
NRZ-type
×8
±37.5%
± (12.5 + (t₀/T₀) × 37.5) %
× 16
±43.7%
± (6.2 + (t₀/T₀) × 43.7) %
× 32
±46.8%
± (3.1 + (t₀/T₀) × 46.8) %
FM-type
×8
±25.0%
± (12.5 + (t₀/T₀) × 25.0) %
× 16
±37.5%
± (6.2 + (t₀/T₀) × 37.5) %
× 32
±43.7%
± (3.1 + (t₀/T₀) × 43.7) %
Notes: 1. Values in this table are theoretical. They do not guarantee the performance of a device.
2. The operating mode is the ratio of the ADPLL operating clock frequency to the bit rate,
as selected by bits DRATE1−0 in MSCI mode register 2.
3. If T₀ is sufficiently long in comparison to t₀, then since t₀/T₀ is approximately zero, the
second term in the bit rate margin formula can be ignored and the first term can be
used as the average bit rate margin.
Ideal
waveform
RXD
(NRZ-type)
RXD
(FM-type)
Actual
waveform
RXD
(NRZ-type)
RXD
(FM-type)
Arbitrary number of bits
1 bit interval
to
To
to/2
To
t
T
t/2
T
Figure 5.42 RXD Input Waveform
Rev. 0, 07/98, page 224 of 453