HD64570 Datasheet, PDF (74/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

3.2.3 Reset Mode
Holding the RESET line low for six or more clock cycles resets all SCA functional modules and
puts the SCA into reset mode. In this mode, the SCA operates as follows:
• The MSCI, DMAC, and timers halt, their internal states are reset, and registers are initialized.
• The A8−A23 and D0−D15 lines go to high impedance and all output lines are initialized to
predefined values.
• WAIT becomes an output line and goes high. Other input/output lines go to the input or high-
impedance state.
The RESET line is sampled at the falling edge of every CLK clock (rising edge in CPU mode 0).
If the RESET line is low on the falling CLK edge (rising edge in CPU mode 0) for six successive
cycles, the SCA enters reset mode after a half clock cycle delay.
Make sure that RESET remains low long enough to be sampled on at least six consecutive falling
edges of CLK (rising edges in CPU mode 0). Correct resetting is not guaranteed if RESET is low
in fewer than six consecutive cycles.
The SCA leaves reset mode when the RESET line goes high. If the RESET line remains high for
five successive falling CLK edges (rising edges in CPU mode 0), the SCA leaves reset mode after
a half clock cycle delay and enters normal operating mode.
Figure 3.2 shows the timing for entering and leaving reset mode.
Rev. 0, 07/98, page 58 of 453