HD64570 Datasheet, PDF (135/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Bits 7−6: Reserved. These bits always read 0 and must be set to 0.
Bit 5 (UDRNC: Underrun State Control): Specifies the transmit operation in underrun state in
byte or bit synchronous mode.
• Asynchronous mode
Reserved. This bit always reads 0 and must be set to 0.
• Byte synchronous mode
UDRNC = 0: Sets the transmitter to idle state in underrun state
UDRNC = 1: Sets the transmitter to idle state after CRC code transmission in underrun state
• Bit synchronous mode
UDRNC = 0: Sets the transmitter to idle state after aborting transmission in underrun state
UDRNC = 1: Sets the transmitter to idle state after FCS (CRC code) and flag transmission in
underrun state
If the UDRNC bit is set to 0 so as to set the transmitter to the idle state after transmitting an abort
frame, a zero may not be inserted immediately before the abort frame. The receiver should thus
discard the data immediately preceding the abort frame.
Bit 4 (IDLC: Idle State Control): Specifies the TXD line output in idle state in byte or bit
synchronous mode.
• Asynchronous mode
Reserved. This bit always reads 0 and must be set to 0.
• Byte synchronous/Bit synchronous mode
IDLC = 0: Sets the TXD line high (mark) in idle state
IDLC = 1: Repeatedly transmits 8-bit idle patterns in the idle pattern register (IDL) in idle
state
Bit 3 (BRK: Send Break): Specifies whether or not to transmit a break in asynchronous mode.
• Asynchronous mode
BRK = 0: Transmits no break (normal operation).
BRK = 1: Transmits a break by setting the TXD line low (space) at the next falling edge of
the transmit clock. The TXD line must be low for two or more character cycles to transmit a
break.
The BRK bit is cleared by a TX reset command.
For details on breaks, see Break Transmission and Detection, in section 5.3.1, Asynchronous
Mode.
• Byte synchronous/Bit synchronous mode
Reserved. This bit always reads 0 and must be set to 0.
Rev. 0, 07/98, page 119 of 453