HD64570 Datasheet, PDF (317/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 6.12 Interrupt Types, Interrupt Sources, and Clearing Procedures
Type
Source
Status Bit Enable Bit Clearing Procedure
Error
interrupt
(DMIA)*¹
FCT overflow (the number of COF
unprocessed interrupts ≥ 16 )
COFE
Write a 1 to the status bit
Buffer underrun/overrun (EDA BOF
value = CDA value and a new
transfer request issued)
BOFE
Write a 1 to the status bit
Normal
end
interrupt
(DMIB)*¹
Frame transfer completion in EOM
chained-block transfer mode*²
EOME
1. Write a 1 to the status
bit*³
2. Issue a frame end
interrupt counter clear
command
DMA transfer completion
EOT
EOTE
Write a 1 to the status bit
FCT: Frame end interrupt counter
CDA: Current descriptor address register
EDA: Error descriptor address register
Notes: 1. Interrupts, once issued, continue to be requested also in DMA initial state or halt state.
2. An interrupt issued at the end of a 1-frame transfer in chained-block multi-frame transfer
mode does not signal the end of a transfer.
3. When FCT is enabled and the FCT value is not 0000, the EOM bit is set to 1. For
details, see sections 6.2.7, DMA Status Register (DSR), 6.2.9, Frame End Interrupt
Counter (FCT), and 6.2.11, DMA Command Register (DCR).
6.6 Reset Operation
When the DMAC is reset, the following steps occur.
• The DMAC enters DMA initial state
• Channel priority becomes 0 > 1 > 2 > 3
• The value of the transfer control registers for specifying addresses and that of the DMA
command register (DCR) become undefined
• The DMA status register (DSR), DMA mode register (DMR), frame end interrupt counter
(FCT), and DMA interrupt enable register (DIR) are initialized as follows:
 Operating mode is single-block transfer mode
 Interrupt status bits and enable bits are cleared
 The FCT value is cleared and FCT is disabled
Rev. 0, 07/98, page 301 of 453