HD64570 Datasheet, PDF (292/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 6.4 Control Registers Used in Memory-to-MSCI Chained-Block Transfer Mode
(transmission) (cont)
Register Receive Buffer Length
Name
(BFL)
Number of 16
bits
Function —
Role in —
DMAC
operation
Register —
update
Register —
updated by
the MPU
Byte Count Register
(BCR)
16
Buffer Address Register
(BAR)
24
Specifies the byte count of
the data to be transferred to
the MSCI.
Writing to this register by
the MPU is inhibited.
Specifies the system
memory address of the
data being transferred to
the MSCI.
Writing to this register by
the MPU is inhibited.
When the contents of this
register equal 0000H,
reading from the current
buffer is completed.
When a transfer request
is issued, data is read
from the address
specified by this register.
The contents of this
register are decremented
each time one byte or one
word is read. When the
buffer is switched, the byte
length specified by the
descriptor is loaded.
The contents of this
register are incremented
each time one byte or one
word is read. When the
buffer is switched, the
next buffer start address
is loaded.
—
—
Table 6.5 shows a memory-to-MSCI chained-block single-frame transfer using four descriptors
and four buffers. In this example, data is not added to the buffers during transmission. As
described in the table, DMA operation of frame 1 ends after steps 1 to 5, when the DMAC enters
DMA initial state. The transfer control register value is retained and thus DMA transfer of frame
2 subsequently starts when the DE bit is set to 1. When frame 2 is completed, the CDA and EDA
contents are equal. Accordingly, the DMAC transfers no data, even if an additional request is
issued from the MSCI, and generates an interrupt DMIA (if enabled).
Rev. 0, 07/98, page 276 of 453